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Semiconductor
August 1997
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HI2304
Triple 8-Bit, 20 MSPS, RGB, 3-Channel D/A Converter
Features
* Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit * Maximum Conversion Speed . . . . . . . . . . . . . . . 20MHz * RGB 3-Channel Input/Output * Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * Low Power Consumption . . . . . . . . . . . . . . . . . . .50mW (330 Load for 1.2VP-P Output) * Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . +3.3V * Low Glitch Noise * Direct Replacement for Sony CXD2304
Description
The HI2304 is a triple 8-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 8-bit, pixel inputs, one each for red, green, and blue video data. A single 3.3V power supply and pixel clock input can be controlled individually, or connected together as one. The HI2304 also has BLANK video control signal. For faster speed and 5.0V operation, refer to the HI1178.
Ordering Information
PART NUMBER HI2304JCQ TEMP. RANGE (oC) -20 to 75 PACKAGE 48 Ld MQFP PKG. NO. Q48.7x7-S
Applications
* Digital TV * Graphics Display * High Resolution Color Graphics * Video Reconstruction * Instrumentation * Image Processing * I/Q Modulation
Pinout
HI2304 (MQFP) TOP VIEW
DVDD DVDD AVDD AVDD AVDD AVDD
VG B0
G0 G0
B0
R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3
1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
R0
R0 IREF VREF AVSS VB DVSS DVSS BCK GCK RCK CE BLK
G6 G7
B2 B3
B1
G5
B4 B5
B0
B6
G4
B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1997
File Number
4116.1
10-1
HI2304 Functional Block Diagram
2 LSBs CURRENT CELLS
(LSB) R0 R1 R2 R3 R4 R5 R6 R7 (LSB) G0
1 2 3 4 5 6 7 8 9 DECODER DECODER LATCHES
47 DVDD 48 DVDD 36 RO 37 RO 27 RCK
6 MSBs CURRENT CELLS
CLOCK GENERATOR 2 LSBs CURRENT CELLS
43 AVDD 44 AVDD 45 AVDD 46 AVDD 38 GO 39 GO 28 GCK
G1 10 G2 11 G3 12 G4 13 G5 14 G6 15 G7 16 (LSB) B0 17 B1 18 B2 19 B3 20 B4 21 B5 22 B6 23 B7 24 DECODER DECODER LATCHES DECODER DECODER LATCHES
6 MSBs CURRENT CELLS
CLOCK GENERATOR 2 LSBs CURRENT CELLS
33 AVSS 30 DVSS 31 DVSS
6 MSBs CURRENT CELLS
40 BO 41 BO 29 BCK 42 VG
CLOCK GENERATOR CURRENT CELLS (FOR FULL SCALE)
+ BLK 25
-
34 VREF 35 IREF
CE 26
BIAS VOLTAGE GENERATOR
32 VB
Pin Descriptions
PIN NO. 1 to 8 9 to 16 17 to 24 SYMBOL R0 to R7 G0 to G7 B0 to B7
1 TO 25
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Digital Input.
DVSS
10-2
HI2304 Pin Descriptions
PIN NO. 25 SYMBOL BLK (Continued) EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Blanking pin. No signal at "H" (Output 0V) Output condition at "L".
25
DVSS
32
VB
DVDD
DVDD
Connect a capacitor of about 0.1F.
32
+
-
DVSS
27 28 29
RCK GCK BCK
27 28 29
DVDD
Clock Pin.
DVSS
30, 31 33 26
DVSS AVSS CE
DVDD
Digital GND. Analog GND. Chip Enable Pin. No signal (Output 0V) at "H" and minimizes power consumption.
26
DVSS
10-3
HI2304 Pin Descriptions
PIN NO. 35 34 42 SYMBOL IREF
AVDD AVDD
(Continued) EQUIVALENT CIRCUIT DESCRIPTION Connect a resistance 16 times "16R" that of output resistance value "R". Set full scale output value. Connect a capacitor of about 0.1F.
AVDD 35 +
VREF VG
-
AVDD AVSS 34 42
AVSS AVSS
43 to 46 37 39 41 36 38 40
AVDD RO GO BO RO GO BO
37 39 41 AVDD
Analog VDD . Current output pin. Voltage output can be obtained by connecting a resistance.
Inverted current output pin. Normally dropped to analog GND.
AVSS AVDD
36 38 40
AVSS
47, 48
DVDD
Digital VDD .
10-4
HI2304
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature (TSTG) . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (IOUT). . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA (Every Each Channel)
Operating Conditions
Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0V to 3.6V DVDD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0V to 3.6V Reference Input Voltage (VREF). . . . . . . . . . . . . . . . . . . . . . . . 1.2V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Resolution Maximum Conversion Speed Linearity Error Differential Linearity Error Full Scale Output Voltage Full Scale Output Ratio (Note 1) Full Scale Output Current Offset Output Voltage Power supply Current Digital Input Current Set Up Time Hold Time Propagation Delay Time Glitch Energy Crosstalk NOTE: 2. Full Scale Output Ratio = H Level L Level
fCLK = 20MHz, VDD = 3.3V, ROUT = 330, VREF = 1.2V, RIRF = 5.1k, TA = 25oC SYMBOL
n
TEST CONDITIONS
MIN 20 -2.5 -0.5 1.12 0 -
TYP 8 1.24 1.5 3.8 15 20 150 53
MAX 2.5 0.5 1.36 3 1 5 -
UNITS Bit MHz LSB LSB V % mA mV mA A A ns ns ns pV/s dB
fMAX INL DNL VFS FSR IFS VOS IDD IIH IIL tS tH tPD GE CT 1MHz Sine Wave Output 14.3MHz, at Color Bar Data input
-5 7 3 -
Full scale voltage of channel ------------------------------------------------------------------------------------------------------------------------------- - 1 Average of the full-scale voltage of the channels
x 100(%).
I/O Chart
(When Full Scale Output Voltage at 2.00V)
INPUT CODE MSB 1 1 1 1 1 1 1 LSB 1 OUTPUT VOLTAGE 1.2V
* * *
1 0 0 0 0 0 0 0 0.6V
* * *
0 0 0 0 0 0 0 0 0V
10-5
HI2304 Timing Diagram
tPW1 tPW1
CLK
tS
tH
tS
tH
tS
tH
DATA
tPD 100%
D/A OUT tPD tPD
50%
0%
Typical Application Circuit
B (BLUE) OUT 330 AVSS G (GREEN) OUT 330 DVDD AVDD 0.1 330 48 47 46 45 44 43 42 41 40 39 38 37 (LSB) 1 2 3 R (RED) IN 4 5 6 7 (MSB) 8 (LSB) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (MSB) (LSB) G (GREEN) IN (MSB) (BCK) 29 (GCK) 28 (RCK) 27 26 25 DVSS HI2304 36 35 34 33 32 0.1 31 30 DVSS CLOCK IN AVSS 1.2V AVDD 1K 5.1K AVSS AVSS AVSS R (RED) OUT
B (BLUE) IN
10-6
HI2304 Notes On Operation
* How to Select the Output Resistance The HI2304 is a current output D/A converter. To obtain the output voltage, connect the resistance to IO pin (RO, GO, BO). For specifications we have: Output Full Scale Voltage VFS = 1.2 [V]. Output Full Scale Current IFS = 3.8 [mA]. Calculate the output resistance value from the relation of VFS = IFS x R. Also, 16 times resistance of the output resistance is connected to reference current pin IREF . In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here, please note that VFS becomes VFS = VREF x 16R/R. R is the resistance connected to IO while R is connected to IREF . Increasing the resistance value can curb power consumption. On the other hand, glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. * Phase Relation Between Data and Clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock, applied from the exterior. Be sure to satisfy the provisions of the set up time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. * VDD , VSS To reduce noise effects, separate analog and digital systems in the device periphery. For VDD pins, both digital and analog, bypass respective GNDs by using a ceramic capacitor of about 0.1F, as close as possible to the pin.
Test Circuits
8-BIT COUNTER WITH LATCH R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 25 BLK 0.1 26 CE 32 VB DVSS HI2304 B0 41 R0 37 330 AVSS G0 39 330 AVSS 330 AVSS AVDD CLK 20MHz SQUARE WAVE 27 RCK 28 GCK 29 BCK VG 42 VREF 34 IREF 35 5.1K AVSS 0.1 1K OSCILLOSCOPE
FIGURE 1. MAXIMUM CONVERSION RATE TEST CIRCUIT
8-BIT COUNTER WITH LATCH
R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 25 BLK
R0 37 330 AVSS G0 39 330 B0 41 AVSS 330 AVSS AVDD OSCILLOSCOPE
DELAY CONTROLLER
0.1
26 CE 32 VB HI2304
DVSS
CLK 1MHz SQUARE WAVE
27 RCK DELAY CONTROLLER 28 GCK 29 BCK
VG 42 VREF 34 IREF 35 5.1K AVSS 0.1 1K
FIGURE 2. SET-UP HOLD TIME GLITCH ENERGY TEST CIRCUIT
10-7
HI2304 Test Circuits
(Continued)
DIGITAL WAVEFORM GENERATOR
ALL "1"
R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 25 BLK
R0 37 330 AVSS G0 39 330 B0 41 AVSS 330 AVSS AVDD SPECTRUM ANALYZER
0.1
26 CE 32 VB HI2304
DVSS
CLK 20MHz SQUARE WAVE
27 RCK 28 GCK 29 BCK
VG 42 VREF 34 IREF 35 5.1K AVSS 0.1 1K
FIGURE 3. CROSSTALK TEST CIRCUIT (See Figure 7)
CONTROLLER
R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 25 BLK 0.1 26 CE 32 VB HI2304 DVSS
R0 37 330 AVSS G0 39 330 B0 41 AVSS 330 AVSS AVDD DVM
CLK 20MHz SQUARE WAVE
27 RCK 28 GCK 29 BCK
VG 42 VREF 34 IREF 35 5.1K AVSS 0.1 1K
FIGURE 4. DC CHARACTERISTICS TEST CIRCUIT
10-8
HI2304 Test Circuits
(Continued)
R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 25 BLK 0.1 26 CE 32 VB HI2304 DVSS B0 41
FREQUENCY DEMULTIPLIER
R0 37 330 AVSS G0 39 330 AVSS 330 AVSS AVDD OSCILLOSCOPE
CLK 1MHz SQUARE WAVE
27 RCK 28 GCK 29 BCK
VG 42 VREF 34 IREF 35 5.1K AVSS 0.1 1K
FIGURE 5. PROPAGATION DELAY TIME TEST CIRCUIT
ALL "1" R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 25 BLK 0.1 26 CE 32 VB HI2304 DVSS B0 41
DIGITAL WAVEFORM GENERATOR
R0 37 330 AVSS G0 39 330 AVSS 330 AVSS AVDD SPECTRUM ANALYZER
ALL "1"
CLK 20MHz SQUARE WAVE
27 RCK 28 GCK 29 BCK
VG 42 VREF 34 IREF 35 AVSS 0.1 1K
SNR: Difference between primary component and secondary distortion.
FIGURE 6. SNR TEST CIRCUIT (See Figure 8)
10-9
HI2304 Typical Performance Curves
80
80
CROSSTALK (dB)
60 SNR (dB)
60
40
40
20
20
0
0 0.1M 1M OUTPUT FREQUENCY (Hz) 10M 0.1M 1M OUTPUT FREQUENCY (Hz) 10M
FIGURE 7. CROSSTALK
FIGURE 8. SNR (DIFFERENCE BETWEEN PRIMARY COMPONENT AND SECONDARY DISTORTION)
OUTPUT FULL SCALE VOLTAGE (V)
1.27 CURRENT CONSUMPTION (mA) -25 0 25 50 75
20
10
1.26
0 AMBIENT TEMPERATURE (oC)
0 10K 100K 1M 10M OUTPUT FREQUENCY (Hz)
FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
FIGURE 10. OUTPUT FREQUENCY vs CURRENT CONSUMPTION
400
GLITCH ENERGY (pV/s)
200
0 200 400 600
FIGURE 11. OUTPUT RESISTANCE vs GLITCH ENERGY
10-10
HI2304 Reference Measurement Condition and Description
AVDD = 3.3V. DVDD = 3.3V. VREF = 1.2V. RIRF = 5.1k. TA = 25oC. Figure 7 and Figure 8 refer to the measurement circuit. Figure 9 is input data = all 1. Figure 10 is input data = output of incremental counter, current consumption is total of 3ch.
10-11

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